1. Field of the Invention:
The invention relates to an arrangement or configuration on a semiconductor substrate in the case where a clock pulse generator for charge transfer arrays such as CCDs (Charge Coupled Devices), BBDs (Bucket Brigade Devices), BCDs (Bulk Charge Transfer Devices) or the like are integrated with the charge transfer arrays and fabricated on the same semiconductor substrate as that of the charge transfer arrays.
2. Description of the Prior Art
A charge transfer device comprises a clock pulse generator circuit driving, through conductor lines, one or more charge transfer arrays, such as charge coupled devices as described, e.g. in U.S. Pat. No. 3,700,932, consisting of an input stage, an output stage, and a plurality of transfer stages. A signal entered from the input stage is sequentially shifted through the transfer stages in synchronism with clock pulses, and is detected at the output stage.
In order to put the charge transfer device into practical use, considering easy handling of the device, easy shielding etc., it is desirable to form and integrate the clock pulse generator circuit on the same substrate as that of the charge transfer array.
On the other hand, since the output signal-to-noise ratio decreases extremely on account of an amplitude change of the clock pulses, a change of the frequency characteristic of the charge transfer array, etc., when the clock frequency of the charge transfer device changes, a differential method, in which charge transfer arrays consisting of two lines are driven so as to compensate for noise, has been proposed. The method is based on the fact that, when the charge transfer arrays are driven by the same clock pulses and the difference between two output signals is formed, in-phase noises can be compensated.
When a clock pulse generator circuit for the charge transfer arrays based on the differential method is to be integrated on the same substrate as that of the charge transfer arrays, the clock pulse generator circuit can be arranged either in the vertical direction or in the horizontal direction with respect to the charge transfer arrays. However, the arrangement in which the clock pulse generator circuit is disposed in the horizontal direction is better than the arrangement in which the clock pulse circuit is disposed in the vertical direction in light of the purpose of the differential method, because it is apparent that the former can reduce noises more than the latter.
Even in the case of the latter, however, there are the problems mentioned below.
(1) The charge transfer array itself is an elongated device. When the clock pulse generator circuit is further provided in the horizontal direction, the shape of a chip becomes more elongated, and chip attachment, package etc. becomes costly. PA1 (2) The number of intersections between pulse lines and intersections between input signal lines and the pulse lines are large, so that noises are large. In addition, noises enter asymmetrically with respect to the pulse waveform, so that the effect of the differential method diminishes. PA1 (3) The charge transfer device is a capacitive load (50 - 200 pF per phase), and a power of about 0.4 - 1 W is consumed in the entire clock pulse circuit to drive the charge transfer arrays at high speed (.about. 10 MHz). When such clock pulse generator circuit is formed as one unit, the temperature rise in the vicinity of the clock pulse generator circuit is large, the current of a MOS transistor constituting the clock pulse circuit decreases, the conductance is lowered, and the performance of the clock pulse circuit is degraded. PA1 (4) Even when the clock pulse generator circuit is carefully designed, the thermal distribution becomes asymmetric, and temperature increases of the charge transfer arrays differ. This induces asymmetry in the leakage current, and results in increasing noises.